A conventional data communication system comprises a first and a second node interconnected by an intervening serial data communication channel, such as a wire link or optical fiber link. The first node typically comprises a first data processing unit (DPU) connected to a transmitter. The output of the transmitter is connected to the channel. The transmitter typically comprises a data path for supplying serial input data from the first DPU to the channel. Likewise, the receiver typically comprises a data path for supplying data received from the channel to the second DPU.
The receiver typically comprises an up channel driver connected to the channel. Similarly the transmitter typically comprises an up channel receiver connected to the channel. The up channel driver and the up channel receiver, together with the channel, constitute an up channel communication subsystem for providing communication between the receiver and the transmitter. The up channel communication subsystem is typically employed by the receiver to send control data to the transmitter. The first DPU typically supplies control signals to the transmitter. Similarly, the second DPU typically supplies control signals to the receiver. The first node also typically comprises a receiver. Likewise, the second node also typically comprises a transmitter. In each node, the transmitter and the receiver are typically integrated into a unitary transceiver. The first and second nodes may comprise server computer systems in a data communication network.
In operation, data is serially communicated between the first and second nodes via the channel. The transmitter and receiver each typically comprise a serializer-deserializer (SERDES). In operation, the SERDES in the transmitter converts parallel data words into a serial bit stream for communication on the channel. In the receiver, the SERDES converts a bit stream received from the channel into parallel data words. Each SERDES is typically implemented in one or more integrated circuits. As improvements continue to be made in semiconductor technology, the performance of such integrated circuits continues to increase. Accordingly, each successive generation of SERDES is capable of handling an increased data rate.
The receiver comprises a signal detector. The signal detector comprises an amplifier and a comparator. In operation, the output from the amplifier is compared to a threshold value Vt by the comparator. The comparator has a hysteresis between its upper and lower switching thresholds. If the hysteresis width is 2Vh, then the upper and lower switching thresholds of the comparator are Vt−Vh and Vt+Vh. Signals less than the lower threshold are determined as invalid. Signals greater than the upper threshold are determined to be valid. There is a band of uncertainty between the upper and lower thresholds where the signal cannot be determined to be good or bad. The width of this band depends on range of circuit parameters including, for example, offset voltage. U.S. Pat. No. 6,897,712 and US20050093582A1 describe examples of conventional signal detectors.
Performance improvement techniques such as Decision Feedback Equalization (DFE) are employed in many data communication system to counter losses within the channel in the interests of achieving higher data rates. A receiver for performing DFE typically comprises an automatic gain control (AGC) loop having a variable gain amplifier (VGA). US20020136251 describes an example of an AGC for use with a signal detector. WO03030356A2 describes another conventional example of an AGC. US20050009483A1 describes an example of conventional AGC calibration.
A typical receiver comprises a signal detector and a cable detector. In operation, the signal detector detects the presence and absence of valid signals on the channel. A valid or good signal is a signal having a pulse height exceeding a preset upper threshold. An invalid or bad signal is a signal having a pulse height below a preset lower threshold. Depending on circuit accuracy, there is normally a region of uncertainty between the lower and upper thresholds in which a signal cannot be declared bad or good. This region is conventionally specified by end users.
In operation, the signal detector enhances the receiver by preventing the processing of potentially unreliable signals.
Specifically, in response to detection of the received signal level falling below the lower threshold, the signal detector alerts the receiving node to stop data processing. In such a situation, the received data may not be valid for one or more of a variety of reasons, including, without limitation, excessive noise in the received signal, excessive cross talk between channels, and signal loss in the channel. The cable detector can be employed to detect whether a cable carrying the channel is unplugged or shorted.
It is increasingly difficult to integrate this functionality into receiver designs as performance increases and available silicon area reduces. There is continuing demand for increasing the data rate that the signal detector is capable of handling without adversely affecting the accuracy with which the signal detector applies the upper and lower thresholds. These thresholds are relatively small. Therefore, the signal detector typically comprises an amplifier to amplify the input signal to facilitate subsequent threshold detection. As performance increases, the power consumption, and area of the amplifier also tends to increase. It would be desirable to improve signal detection performance and simultaneously to alleviate pressure for increased silicon real estate occupancy and power.